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CXD3521GG
Interface and Driver IC for LCD
Description The CXD3521GG is an interface and driver IC for the color LCD module ACX704AKM/BKM. Features * Generates the color LCD module ACX704AKM/BKM drive pulse. * Supports standby mode * Built-in 9-channel reference voltage driver * Built-in common voltage driver Applications PDA, compact LCD monitor, etc. Structure Silicon gate CMOS IC 128 pin TFBGA (Plastic)
Absolute Maximum Ratings (Ta = 25C) * Supply voltage 1 VDD1 VSS - 0.3 to +4.6 * * * *
V Supply voltage 2 VDD2 VSS - 0.3 to +6.0 V Input voltage VI VSS - 0.3 to VDD + 0.3 V Output voltage VO VSS - 0.3 to VDD + 0.3 V Storage temperature Tstg -55 to +125 C
Recommended Operating Conditions 3.0 to 3.6 * Supply voltage 1 VDD1 * Supply voltage 2 VDD2 4.7 to 5.3 * Operating temperature Topr -25 to +75
V V C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E01408-PS
CXD3521GG
Block Diagram
VDD1 (3.3V) VSS1 (GND) C10, J6, L11, M1 B11, G9, L2 R3 H12 R2 H11 R1 H10 R0 H9 G3 J12 G2 J11 G1 J10 G0 J9 B3 K12 B2 K11 B1 K10 B0 K9 MCK L12 PCI G11 Hsync/DENB G12 SLIN E10 TESTP M12 TEST A12 Vsync G11 V Counter Delay H Timing Pulse GEN. E9 PCO Power CTR. H4, H3 HST1, XHST1 Delay H Counter H2, H1 HST2, XHST2 K2, K1 HCK1, XHCK1 J2, J1 HCK2, XHCK2 D8, A7, B7, C7 XB32, XB22, XB12, XB02 M5, L5, K5, J5 B12, C12, D12, A11 D9, A8, B8, C8 J8, M7, L7, K7 M4, L4, M3, L3 C11, D11, A10, B10 XG31, XG21, XG11, XG01 G32, G22, G12, G02 XG32, XG22, XG12, XG02 B31, B21, B11, B01 XB31, XB21, XB11, XB01 B32, B22, B12, B02 Serial/Parallel Transform Block M11, L10, M10, M9 J7, M6, L6, K6 F12, F11, E12, E11 D10, A9, B9, C9 L9, M8, L8, K8 R31, R21, R11, R01 XR31, XR21, XR11, XR01 R32, R22, R12, R02 XR32, XR22, XR12, XR02 G31, G21, G11, G01
G4, G3, OE1, XOE1, G2, G1 OE2, XOE2 M2, L1 VST, XVST
CLR F9
V Timing Pulse GEN.
J4, J3
VCK, XVCK
K4, K3 ENB, XENB Timing Generator Block VDD2 (5.0V) VSS1 (GND) B2, D2, D7 B4, D3, F4 F3 V0 F10 TESTO
E2 V1 VH1 F2 VL1 F1 VH2 E1 VL2 E3 Resistor Array Block D1 V3 E4 V2
VRFSTB A1
C1 V4
D4 V5
C3 V6 VH6 C2 VL6 B1 B3 V7
VH8 A2 VL8 C4
D5 V8
A3 VCOM Reference Voltage Driver Block
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CXD3521GG
Pin Configuration (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
A VRFSTB VH8 VCOM TESTL1 TESTL7 TESTL5 XB22 XG22 XR22 B12 G02 TEST1
B VL6 VDD2 V7 VSS2 TESTL8 TESTL4 XB12 XG12 XR12 B02 VSS1 G32
C V4 VH6 V6 VL8 TESTL2 TESTL6 XB02 XG02 XR02 VDD1 B32 G22
D V3 E VH2 F VL1 G XOE2 H XHST2 J XHCK2 K XHCK1 L XVST M VDD1 VST XB11 XB31 XG31 XR21 B21 G21 R01 R11 R31 TESTP VSS1 XB01 XB21 XG21 XR11 B11 G11 G31 R21 VDD1 MCK HCK1 XENB ENB XG11 XR01 B01 G01 B0 B1 B2 B3 HCK2 XVCK VCK XG01 VDD1 XR31 B31 G0 G1 G2 G3 HST2 XHST1 HST1 R0 R1 R2 R3 OE2 XOE1 OE1 VSS1 PCI Vsync Hsync/ DENB VH1 V0 VSS2 CLR TESTO R22 R32 V1 VL2 V2 PCO SLIN R02 R12 VDD2 VSS2 V5 V8 TESTL3 VDD2 XB32 XG32 XR32 B22 G12
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CXD3521GG
Pin Description Pin No. B11 G9 L2 C10 J6 L11 M1 F9 H12 H11 H10 H9 J12 J11 J10 J9 K12 K11 K10 K9 G12 G11 L12 G10 E10 F10 E9 M11 L10 M10 M9 L9 M8 L8 K8 J8 Symbol VSS1 VSS1 VSS1 VDD1 VDD1 VDD1 VDD1 CLR R3 R2 R1 R0 G3 G2 G1 G0 B3 B2 B1 B0 Hsync/DENB Vsync MCK PCI SLIN TESTO PCO R31 R21 R11 R01 G31 G21 G11 G01 B31 I/O -- -- -- -- -- -- -- I I I I I I I I I I I I I I I I I I O O O O O O O O O O O GND (Logic) GND (Logic) GND (Logic) Power supply (3.3V) Power supply (3.3V) Power supply (3.3V) Power supply (3.3V) System reset (Cleared at 0V) Red signal input (MSB) Red signal input Red signal input Red signal input (LSB) Green signal input (MSB) Green signal input Green signal input Green signal input (LSB) Blue signal input (MSB) Blue signal input Blue signal input Blue pulse input (LSB) Hsync pulse input/Data enable signal input Vsync pulse input Dot clock input Power control signal input Sync input signal mode selector switch Test output (Leave it open.) Power control signal output Red signal output Red signal output Red signal output Red signal output Green signal output Green signal output Green signal output Green signal output Blue signal output Description Input pin for open status -- -- -- -- -- -- -- UP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
UP: Pull-up (typ. 160k) -4-
CXD3521GG
Pin No. M7 L7 K7 J7 M6 L6 K6 M5 L5 K5 J5 M4 L4 M3 L3 M12 A12 M2 L1 K4 K3 J4 J3 K2 K1 J2 J1 H4 H3 H2 H1 G4 G3 G2 G1 D8 A7
Symbol B21 B11 B01 XR31 XR21 XR11 XR01 XG31 XG21 XG11 XG01 XB31 XB21 XB11 XB01 TESTP TEST VST XVST ENB XENB VCK XVCK HCK1 XHCK1 HCK2 XHCK2 HST1 XHST1 HST2 XHST2 OE1 XOE1 OE2 XOE2 XB32 XB22
I/O O O O O O O O O O O O O O O O I I O O O O O O O O O O O O O O O O O O O O Blue signal output Blue signal output Blue signal output
Description
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DWN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
R31 signal inversion output R21 signal inversion output R11 signal inversion output R01 signal inversion output G31 signal inversion output G21 signal inversion output G11 signal inversion output G01 signal inversion output B31 signal inversion output B21 signal inversion output B11 signal inversion output B01 signal inversion output Test input (Connect to GND.) Test input (Connect to GND.) VST pulse output VST pulse inversion output ENB pulse output ENB pulse inversion output VCK pulse output VCK pulse inversion output HCK1 pulse output HCK1 pulse inversion output HCK2 pulse output HCK2 pulse inversion output HST1 pulse output HST1 pulse inversion output HST2 pulse output HST2 pulse inversion output OE1 pulse output OE1 pulse inversion output OE2 pulse output OE2 pulse inversion output B32 signal inversion output B22 signal inversion output -5-
DWN: Pull-down (typ. 180k)
CXD3521GG
Pin No. B7 C7 D9 A8 B8 C8 D10 A9 B9 C9 C11 D11 A10 B10 B12 C12 D12 A11 F12 F11 E12 E11 B4 D3 F4 B2 D2 D7 A4 C5 D6 B6 A6 A5 C6 B5 F3
Symbol XB12 XB02 XG32 XG22 XG12 XG02 XR32 XR22 XR12 XR02 B32 B22 B12 B02 G32 G22 G12 G02 R32 R22 R12 R02 VSS2 VSS2 VSS2 VDD2 VDD2 VDD2 TESTL1 TESTL2 TESTL3 TESTL4 TESTL5 TESTL6 TESTL7 TESTL8 V0
I/O O O O O O O O O O O O O O O O O O O O O O O -- -- -- -- -- -- O O I I O I I I O
Description B12 signal inversion output B02 signal inversion output G32 signal inversion output G22 signal inversion output G12 signal inversion output G02 signal inversion output R32 signal inversion output R22 signal inversion output R12 signal inversion output R02 signal inversion output Blue signal output Blue signal output Blue signal output Blue signal output Green signal output Green signal output Green signal output Green signal output Red signal output Red signal output Red signal output Red signal output GND (Analog) GND (Analog) GND (Analog) Power supply (5.0V) Power supply (5.0V) Power supply (5.0V) Test output (Leave it open.) Test output (Leave it open.) Test input (Connect to GND.) Test input (Connect to GND.) Test output (Leave it open.) Test input (Connect to GND.) Test input (Connect to GND.) Test input (Connect to GND.) V0 output -6-
Input pin for open status -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DWN -- -- -- -- -- --
DWN: Pull-down (typ. 180k)
CXD3521GG
Pin No. E2 E4 D1 C1 D4 C3 B3 D5 A3 A1 F2 F1 E1 E3 C2 B1 A2 C4 V1 V2 V3 V4 V5 V6 V7 V8
Symbol
I/O O O O O O O O O O I I I I I I I I I V1 output V2 output V3 output V4 output V5 output V6 output V7 output V8 output VCOM output
Description
Input pin for open status -- -- -- -- -- -- -- -- -- DWN -- -- -- -- -- -- -- --
VCOM VRFSTB VH1 VL1 VH2 VL2 VH6 VL6 VH8 VL8
Reference voltage driver on/off selector switch VH1 input VL1 input VH2 input VL2 input VH6 input VL6 input VH8 input VL8 input
DWN: Pull-down (typ. 180k)
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CXD3521GG
Electrical Characteristics (Serial/parallel conversion block, timing generator block) DC Characteristics Item Supply voltage Current consumption Input voltage 1 Symbol VDD1 IDD1 VIH1 VIL1 Vt+ Input voltage 2 Vt- | IIL1 | Input current 1 | IIH1 | Input current 2 Input current 3 | IIL2 | | IIH2 | | IIL3 | | IIH3 | VDD1 VDD1 MCK, VRFSTB, TESTL1, TESTL2, TESTL3, TESTL4 All input pins excluding MCK, VRFSTB, TESTL1, TESTL2, TESTL3, TESTL4 R0, R1, R2, R3, G0, G1, G2, G3, B0, B1, B2, B3, Hsync/DENB, Vsync, MCK, PCI CLR TEST, TESTP SLIN , Applicable pins Conditions -- No load, Ta = 25C VDD1 = 3.3V, MCK: 5.62MHz CMOS input cell -- CMOS Schmitt trigger input cell VI = 0V VI = VDD VI = 0V VI = VDD VI = 0V VI = VDD R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, IOL1 = 4.0mA G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, IOH1 = -4.0mA VST, XVST, ENB, XENB, OE1, XOE1, OE2, XOE2, TESTO HST1, XHST1, HST2, XHST2, VCK, XVCK, PCO HCK1, XHCK1, HCK2, XHCK2 IOL2 = 6.0mA IOH2 = -6.0mA IOL3 = 10.0mA -- 0.15VDD1 -- -- 10 -- -- 10 -- -- -- -- -- -- -- -- -- 0.2VDD1 0.75VDD1 V -- 1.0 A 1.0 100 3.0 3.0 100 A A (VDD1 = 3.0 to 3.6V, Ta = -25 to +75C) Min. 3.0 -- 0.7VDD1 Typ. 3.3 1.5 -- Max. 3.6 -- -- V Unit V mA
VOL1
--
--
0.2
Output voltage 1
V
VOH1
VDD - 0.8
--
--
VOL2 Output voltage 2 VOH2 VOL3 Output voltage 3 VOH3
-- VDD - 0.8 --
-- -- -- --
0.2 V -- 0.4 -- V
IOH3 = -10.0mA VDD - 0.8
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CXD3521GG
AC Characteristics Item HCK/HST time difference Symbol tHST-HCKU tHST-HCKD Applicable pins HCK1, HCK2, XHCK1, XHCK2, HST1, HST2, XHST1, XHST2 R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32 HCK1, HCK2, XHCK1, XHCK2, HST1, HST2, XHST1, XHST2 VCK, XVCK, VST, XVST, ENB, XENB, OE1, OE2, XOE1, XOE2, PCO, TESTO HCK1, HCK2, XHCK1, XHCK2, R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32 HCK1, HCK2, XHCK1, XHCK2, VCK, XVCK
(VDD = 3.0 to 3.6V, Ta = -25 to +75C) Conditions1 -- Min. -- Typ. -- Max. 152 Unit ns
Data output rise time
tRD
GND - VDD (0 - 90%)
--
--
35
ns VDD - GND (100 - 10%)
Data output fall time
tFD
--
--
35
Horizontal pulse output rise time Horizontal pulse output fall time Vertical pulse output rise time Vertical pulse output fall time
tRHP tFHP tRVP tFVP
GND - VDD (0 - 90%) VDD - GND (100 - 10%) GND - VDD (0 - 90%) VDD - GND (100 - 10%)
-- -- -- --
-- -- -- --
35 ns 35 50 ns 50
HCK1, HCK2, XHCK1, XHCK2/ DATA setup time
tSTP
3
35
55
100
ns
HCK, VCK duty
dHCK dVCK
4
48
50
52
%
1 Load capacitance CL of each output pin is shown below. * R01, R11, R21, R31, R02, R12, R22, R32, XR01, XR11, XR21, XR31, XR02, XR12, XR22, XR32, G01, G11, G21, G31, G02, G12, G22, G32, XG01, XG11, XG21, XG31, XG02, XG12, XG22, XG32, B01, B11, B21, B31, B02, B12, B22, B32, XB01, XB11, XB21, XB31, XB02, XB12, XB22, XB32, OE1, XOE1, OE2, XOE2, TESTO, ENB, XENB : CL = 70pF * HCK1, HCK2, XHCK1, XHCK2 : CL = 180pF * VCK, XVCK : CL = 150pF * HST1, HST2, XHST1, XHST2, VST, XVST, PCO : CL = 100pF 2 Absolute value of the time difference of the change point at HST1, XHST1, HCK1 and XHCK1 (50%) is within 15ns. Similarly, absolute value of the time difference of the change point at HST2, XHST2, HCK2 and XHCK2 (50%) is within 15ns. 3 tSTP: tST1D, tST1U, tST2D, tST2U 4 dHCK = (tHH/(tHH + tHL)) x 100, dVCK = (tVH/(tVH + tVL)) x 100 -9-
CXD3521GG
Timing Definition Horizontal System
tHH tHL VDD1 HCK1 50% 50% 50% GND VDD1 XHCK1 50% 50% GND tH tH
VDD1 HCK2 50% 50% GND VDD1 XHCK2 50% 50% GND tH tH
VDD1 HST1 (HST2) 50% GND VDD1 XHST1 (XHST2) 50% GND
VDD1 HCK1 (HCK2) 50% GND
VDD1 XHCK1 (XHCK2) tHST-HCKU 50% GND tHST-HCKD
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CXD3521GG
Vertical System
tVH tVL VDD1 VCK 50% 50% 50% GND VDD1 XVCK 50% 50% GND tV tV
DATA
VDD1 HCK1 50% 50% GND VDD1 XHCK1 50% 50% GND
VDD1 HCK2 50% 50% GND VDD1 XHCK2 50% 50% GND
VDD1 DATA GND tST1D tSTX1U tST2D tSTX2U tST1U tSTX1D tST2U tSTX2D
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CXD3521GG
PCI, PCO These pins control to turn power on/off of the ACX704AKM/BKM when the LCD is turned on/off. Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM/BKM.
Power-on Sequence * Raise and fall VDD1 and VDD2 simultaneously (within 10ms) * Input the input signal1 for 1 field (Min.), and then raise PCI. * After PCI becomes high, latch is performed twice at Vsync. When both of them are high, PCO output is changed from low to high. (Turn the power on of the ACX704AKM/BKM at this timing.) Also, effective screen is displayed after two fields of entire white display from this timing.
10ms VDD1 VDD2 CLR VDD1 0 VDD2 0 VDD1 0 PCI Low 1 2 High
PCO Pulse2
Low
High
Low
Active
DATA (out)
Low
White Data
Valid
Vsync
Low
DENB MCK Hsync DATA (in)
Low
Low
Active
1 field (min.)
1 field (min.)
2 fields
1 Hsync, Vsync, DENB, MCK, DATA 2 HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB, OE1, XOE1, OE2, XOE2, TESTO, (FRP)
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CXD3521GG
Power-off Sequence (Standby) * When LCD is off, LCD is turned off after entire white display.
10ms
Standby Mode PCI High Low
PCO VDD1
High
Low VDD1 0 VDD2 0
VDD2 Low
DATA
Valid
All Data: High (XDATA: Low)
Pulse1
Active
Low
Vsync DENB 3 fields MCK Hsync DATA (in) Active 10 fields
Low Low
Low
1 HST1, XHST1, HST2, XHST2, HCK1, XHCK1, HCK2, XHCK2, VST, XVST, VCK, XVCK, ENB, XENB, OE1, XOE1, OE2, XOE2, TESTO, (FRP)
SLIN This is a selector switch for sync input signal mode. SLIN: Low Hsync + Vsync Mode. SLIN: High DENB ONLY Mode. (Vsync is invalid.)
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Horizontal Direction Input Signal Timing Chart
352 dots 310 MCK Hsync1 16 dots DENB1 32 dots DATA
307 308 309 310 311 312 313 314 315 316 317 318 319 320 1 2 3 4 5 6 7 8 9 10 11
315
320
325
330
335
340
345
350
0
5
4 dots (min.) 16 dots
tch MCK thss Hsync1 tclk
tcl
- 14 -
DENB1
thsw tdes tdeh
DATA
1 tds 1 Input either Hsync + Vsync or DENB as sync input signal. tdh
2
320
Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = -25 to +75C) Item MCK frequency MCK low, high pulse width DATA setup time DATA hold time DENB setup time DENB hold time Hsync setup time Hsync low pulse width Symbol ftch Min. 3MHz -- 10ns 15ns 10ns 15ns 10ns 4tclk Typ. 5.58MHz 0.5tclk -- -- -- -- -- -- Max. 8MHz -- -- -- --
CXD3521GG
tch, tcl tds tdh tdes tdeh thss thsw
-- -- 16tclk
Vertical Direction Input Signal Timing Chart
264 lines 230 Hsync1 235 240 245 250 255 260 0 5 10 15
Vsync1 10 lines DENB1 14 lines
Hsync1
(1) tvhde
(2)
(14)
(15)
- 15 -
Vsync1
tvsw DENB1
DATA
1st Line
1 Input either Hsync + Vsync or DENB as sync input signal.
Input Signal AC Characteristics (VDD1 = 3.0 to 3.6V, Ta = -25 to +75C) Item Hsync falling edge Vsync falling edge Vsync low pulse width Symbol Min. 3tclk 2 lines Typ. -- -- Max.
CXD3521GG
tvhde tvsw
352tclk 14 lines
Horizontal Direction Timing Chart
280 MCK 16 dots Hsync DENB
Input
352 dots 290 300 310 320 330 340 0 10 20
16 dots 32 dots
123456789
316 317 318 319 320
DATA
Output
R/G/B 01 to 31 R/G/B 02 to 32 HST1 XHST1 HCK1 XHCK1 HST2
270 272 274 276 278 280 282 284 286 288 290 292 294 296 298 300 302 304 306 308 310 312 314 316 318 320 269 271 273 275 277 279 281 283 285 287 289 291 293 295 297 299 301 303 305 307 309 311 313 315 317 319
2 1
4 3
6 5
8 7
10 12 14 16 18 20 22 24 9 11 13 15 17 19 21 23
344
4 dots
348
342 4 dots 346
- 16 -
XHST2 HCK2 XHCK2 OE1 XOE1 OE2 XOE2 304 ENB XENB 350 VST XVST 334 VCK 0 320 0 328 340
CXD3521GG
334 XVCK 334 FRP
Vertical Direction Timing Chart
264 lines 240 Hsync Vsync 10 lines 245 250 255 260 0 5 10 15 20
Input
DENB
14 lines
Output
VST XVST
VCK XVCK
- 17 -
ENB XENB OE1 XOE1 OE2 XOE2 FRP (O)1 FRP (E)1
CXD3521GG
1 FRP (O): FRP pulse at odd field. FRP (E): FRP pulse at even field.
CXD3521GG
Reference Voltage Driver Block Block Diagram
VDD2 (5.0V)
VDD2
VH0 VL0 VH1 VL1 VH2 VL2 VH3 VL3 VH4 VL4 VH5 VL5 VH6 VL6 VH7 VL7 VH8 VL8 V8 VCOM V7 V6 V5 V4 V3 V2 V1 V0
VSS2 Resistor array VRFSTB FRP1 Level Shift Level Shift
VSS2
1 Internal pulse of the logic block
Electrical Characteristics (Reference voltage driver block) Resistor array output voltage Item VH0 VH1 VH2 VH3 VH4 VH5 VH6 VH7 VH8 Min. -- -- -- -- -- -- -- -- -- Typ. 4.800 3.900 3.325 2.950 2.600 2.250 1.950 1.500 0.500 Max. -- -- -- -- -- -- -- -- -- - 18 - V Unit Item VL0 VL1 VL2 VL3 VL4 VL5 VL6 VL7 VL8 (VDD1 = 3.3V, VDD2 = 5.0V, Ta = 25C) Min. -- -- -- -- -- -- -- -- -- Typ. 0.200 1.100 1.675 2.050 2.400 2.750 3.050 3.500 4.500 Max. -- -- -- -- -- -- -- -- -- V Unit
CXD3521GG
AC, DC Characteristics Item Supply voltage Current consumption Symbol VDD2 IDD2 Conditions -- Input voltage = 2.5V, During no load Input voltage = 4.8V Input voltage = 0.2V
(VDD1 = 3.3V, VDD2 = 5.0V, Ta = -25 to +75C) Min. 4.7 -- -0.15 -0.15 0.985 VDD2 - 1.0 -- VDD2 - 0.1 -- -- -- -- -- -- -- -- Typ. 5.0 3.4 -- -- -- -- -- -- -- -- 5 15 -- -- -- -- Max. 5.3 6.0 0.15 0.15 -- -- GND + 1.0 -- GND + 0.1 20 10 -- 10 10 6 6 Unit V mA A A V/V V V V V mV mV s s s s
VH, VL input current high IIH VH, VL input current low Voltage gain Output voltage high Output voltage low COM output voltage high COM output voltage low Offset voltage Load regulation Output impedance Settling time 1 Settling time 2 Settling time 3 Settling time 4 IIL AV VOH VOL VCOH VCOL VOFF VO RIMP
Input voltage = 0.2 to 4.8V ISOURCE = 10mA ISINK = 10mA ISOURCE = 10mA ISINK = 10mA Rs = 10k Input voltage = 0.2 to 4.8V ISOURCE = 10mA ISINK = 10mA V0 to V8 Measurement circuit 1 Measurement circuit 1 Measurement circuit 2 Measurement circuit 2
ts1 ts2 ts3 ts4
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CXD3521GG
Measurement Circuit Measurement circuit 1
4.8V 0.2V
VH VL
15 Measuring point V0 to V8 30nF
Measurement circuit 2
5.0V 0V VCOM 30nF
Measuring point
FRP (internal pulse)
50% ts1 90%
50% ts2
Output (V0 to V8) 10%
90% Output (VCOM) 10% ts3 ts4
VRFSTB This is a selector switch for reference voltage driver output on/off. VRFSTB: Low V0 to V8 and VCOM are GND level. VRFSTB: High V0 to V8 and VCOM are active.
- 20 -
CXD3521GG
Application Circuit
To DC-DC Converter1
To ACX704AKM/BKM VDD2 VDD1
A2 A3 B3 C4 D5 A4 C5 B4 B5 B6 D6 A5 C6 A6 D7 C7 B7 A7 D8 C8 B8 A8 D9 C9 B9 A9 D10 B10 A10 D11 C11 C10
TESTL1 TESTL2 XB02 XB12 XB22 TESTL8 TESTL4 TESTL3 TESTL6 TESTL7 TESTL5 XB32 VSS2 VDD2 XR02 XR12 XR22 VCOM XG02 XG12 XG22 XG32 XR32 VDD1 V7 V8 B02 B12 VL8 B22 VH8 B32
A1 VRFSTB B1 VL7 B2 VDD2 C1 V4 C2 VH7 C3 V6 D1 V3 D2 VDD2 D3 VSS2 D4 V5 E1 VH2 E2 V1 E3 VL2
To ACX704AKM/BKM
TEST A12 VSS1 B11 G02 A11 G12 D12 G22 C12 G32 B12 R02 E11 R12 E12 R22 F11 R32 F12 PCO E9 SLIN E10 CLR F9 TESTO F10 VSS1 G9 PCI G10 Vsync G11 Hsync/DENB G12 R0 H9 R1 H10 R2 H11 R3 H12 G0 G1 J10 G2 J11 G3 J12 B0 K9 B1 K10 B2 K11 B3 K12 MCK L12 VDD1 L11 VDD1
TESTP XENB XVST XG01 XG11 XG21 XG31 XR01 XR11 XR21 XR31 XB01 XB11 XB21 XB31 VDD1 VDD1 VSS1 ENB VST G01 G11 G21 G31 R01 R11 R21 R31 B01 B11 B21 B31 Input To ACX704AKM/BKM
E4 V2 F1 VL0 F2 VH0 F3 V0 F4 VSS2 G1 XOE2 G2 OE2 G3 XOE1 G4 OE1 H1 XHST2 H2 HST2 H3 XHST1 H4 HST1 J1 XHCK2 J2 HCK2 J3 XVCK J4 VCK K1 XHCK1 K2 HCK1
J9
M1 L2 M2 L1 K4 K3 L3 M3 L4 M4 J5 K5 L5 M5 K6 L6 M6 J7 J6 K7 L7 M7 J8 K8 L8 M8 L9 M9 M10 L10 M11 M12
To ACX704AKM/BKM
VDD1
1 Connect PCO to DC-DC converter that can control power on/off of the ACX704AKM/BKM.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
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CXD3521GG
Package Outline
Unit: mm
128PIN TFBGA (PLASTIC)
11.0 0.3 SA
11.0
x4
0.20 10.6 0.1
0.2
S
S
0.1
S 0.8 A 1.1
M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 128 - 0.5 0.05
B
0.08 M
0.8
1.1
SAB
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE TFBGA-128P-061 P-TFBGA128-11x11-0.8 TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS SOLDER 0.22g ORGANIC SUBSTRATE
0.4 0.05
1.2 MAX
0.3
SB
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Sony Corporation

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